\doxysection{GPIO\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_g_p_i_o___type_def}{}\label{struct_g_p_i_o___type_def}\index{GPIO\_TypeDef@{GPIO\_TypeDef}}


General Purpose I/O.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_ac2505d096b6b650f1647b8e0ff8b196b}{MODER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a910885e4d881c3a459dd11640237107f}{OTYPER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a0d233d720f18ae2050f9131fa6faf7c6}{OSPEEDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a44ada3bfbe891e2efc1e06bda4c8014e}{PUPDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_acf11156409414ad8841bb0b62959ee96}{IDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a6fb78f4a978a36032cdeac93ac3c9c8b}{ODR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_acd6f21e08912b484c030ca8b18e11cd6}{BSRR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a95a59d4b1d52be521f3246028be32f3e}{LCKR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_g_p_i_o___type_def_a2245603433e102f0fd8a85f7de020755}{AFR}} \mbox{[}2\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
General Purpose I/O. 

\label{doc-variable-members}
\Hypertarget{struct_g_p_i_o___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_g_p_i_o___type_def_a2245603433e102f0fd8a85f7de020755}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!AFR@{AFR}}
\index{AFR@{AFR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AFR}{AFR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a2245603433e102f0fd8a85f7de020755} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+AFR\mbox{[}2\mbox{]}}

GPIO alternate function registers, Address offset\+: 0x20-\/0x24 \Hypertarget{struct_g_p_i_o___type_def_acd6f21e08912b484c030ca8b18e11cd6}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!BSRR@{BSRR}}
\index{BSRR@{BSRR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BSRR}{BSRR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_acd6f21e08912b484c030ca8b18e11cd6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+BSRR}

GPIO port bit set/reset, Address offset\+: 0x18 \Hypertarget{struct_g_p_i_o___type_def_acf11156409414ad8841bb0b62959ee96}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!IDR@{IDR}}
\index{IDR@{IDR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDR}{IDR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_acf11156409414ad8841bb0b62959ee96} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+IDR}

GPIO port input data register, Address offset\+: 0x10 \Hypertarget{struct_g_p_i_o___type_def_a95a59d4b1d52be521f3246028be32f3e}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!LCKR@{LCKR}}
\index{LCKR@{LCKR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LCKR}{LCKR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a95a59d4b1d52be521f3246028be32f3e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+LCKR}

GPIO port configuration lock register, Address offset\+: 0x1C \Hypertarget{struct_g_p_i_o___type_def_ac2505d096b6b650f1647b8e0ff8b196b}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!MODER@{MODER}}
\index{MODER@{MODER}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MODER}{MODER}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_ac2505d096b6b650f1647b8e0ff8b196b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+MODER}

GPIO port mode register, Address offset\+: 0x00 \Hypertarget{struct_g_p_i_o___type_def_a6fb78f4a978a36032cdeac93ac3c9c8b}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!ODR@{ODR}}
\index{ODR@{ODR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ODR}{ODR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a6fb78f4a978a36032cdeac93ac3c9c8b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+ODR}

GPIO port output data register, Address offset\+: 0x14 \Hypertarget{struct_g_p_i_o___type_def_a0d233d720f18ae2050f9131fa6faf7c6}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!OSPEEDR@{OSPEEDR}}
\index{OSPEEDR@{OSPEEDR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OSPEEDR}{OSPEEDR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a0d233d720f18ae2050f9131fa6faf7c6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+OSPEEDR}

GPIO port output speed register, Address offset\+: 0x08 \Hypertarget{struct_g_p_i_o___type_def_a910885e4d881c3a459dd11640237107f}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!OTYPER@{OTYPER}}
\index{OTYPER@{OTYPER}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OTYPER}{OTYPER}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a910885e4d881c3a459dd11640237107f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+OTYPER}

GPIO port output type register, Address offset\+: 0x04 \Hypertarget{struct_g_p_i_o___type_def_a44ada3bfbe891e2efc1e06bda4c8014e}\index{GPIO\_TypeDef@{GPIO\_TypeDef}!PUPDR@{PUPDR}}
\index{PUPDR@{PUPDR}!GPIO\_TypeDef@{GPIO\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PUPDR}{PUPDR}}
{\footnotesize\ttfamily \label{struct_g_p_i_o___type_def_a44ada3bfbe891e2efc1e06bda4c8014e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t GPIO\+\_\+\+Type\+Def\+::\+PUPDR}

GPIO port pull-\/up/pull-\/down register, Address offset\+: 0x0C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
